时    间：2015年9月14日周一下午13:30-15:30
地    点：张江校区行政楼315会议室
讲座内容：

Overview of Radiation Effects in Modern Electronics

Duration : 45 minutes
By：Adrian Evans of IROC, France
Location: Room 315, Administration Building
Abstract : This talk is intended to introduce the participant to radiation induced soft errors in electronics. It will cover the basic mechanisms by which upsets are induced by ionizing radiation. It will discuss how the charge induced by an ionizing particle can produce SEUs (single event upsets) in flip-flops and RAMs as well as SETs (single event transients) in combinatorial logic. The various masking factors which prevent the vast majority of faults from propagating will be reviewed. The talk will give the participant an understanding of the overall scale and impact of soft-errors in large SoCs and provide an overview of soft-errors trends in advanced technologies such as FinFETs and FDSOI. Techniques for accelerated testing using lasers and particle beams will also be discussed.

 
The Elusive Optimum: Balancing Reliability, Complexity and Verification

Duration : 30 minutes
By：Adrian Evans of IROC, France
Location: Room 315, Administration Building
Abstract : With the proliferation of the Internet of Things (IoT), intelligent cars and mobile devices, there is an increasing demand for reliability in the SoCs. Classical techniques for high reliability, such as Triple Modular Redundancy (TMR), are simply not applicable to such devices which have stringent power and cost constraints. As a result, low cost approaches to deliver high reliability are required. In many cases, such clever techniques to achieve reliability result in an increase in complexity and thus exacerbate the problem of functional verification. This talk will discuss this three-way trade-off between reliability, complexity and verification. It will highlight the need for new analysis techniques and EDA tools which enable designers to make informed decisions and simultaneously achieve multiple design constraints.

 
Perspectives on the Challenges in Functional Verification of Complex SoCs

Duration : 40 minutes
By：Adrian Evans of IROC, France
Location: Room 315, Administration Building
Abstract : It is widely recognized that functional verification is one of the bottlenecks in the overall design process and bug escapes result in costly re-spins that can seriously impact time to market. The number of functional interactions in a SoC tends to grow with the square of the number of functional blocks, which means that the verification problem is scaling faster than the designs themselves. Almost all SoCs embed complex IPs provided by third parties. At the SoC level, great care is required to ensure that these IPs are integrated correctly, however, this must be done without expending excessive effort re-verifying the IP block. This talk will discuss some of the techniques that can help guide an effective flow for functional verification including the collaborative tools that are necessary to ensure that a large team of verification engineers can work effectively. It will touch on the role of formal verification and it will also discuss some of the criteria for assessing when a design has adequate stability for tape-out.